Using platform-specific performance counters for dynamic compilation

  • Authors:

  • Florian Schneider;Thomas R. Gross

  • Affiliations:

  • Laboratory for Software Technology, Department of Computer Science, ETH Zürich, Zürich, Switzerland;Laboratory for Software Technology, Department of Computer Science, ETH Zürich, Zürich, Switzerland

  • Venue:
  • LCPC'05 Proceedings of the 18th international conference on Languages and Compilers for Parallel Computing
  • Year:
  • 2005

Quantified Score

Hi-index 0.00

Visualization

Abstract

Hardware performance counters provide information about events in the hardware platform (e.g., cache misses, pipeline stalls), in contrast to profiles that capture program properties (e.g., execution frequencies for basic blocks, methods, function calls). As platform architectures become more complex and also more diverse, it is important for a compiler to exploit platform-specific information. A dynamic (JIT) compiler is in the unique position to run on the same platform as the target application, but in practice, exploiting the wealth of information available through performance counters is far from easy. If a JIT compiler is to use performance counter information, this information must be fine-grained (e.g., attributing cache misses to a single load instruction) and must be obtainable without undue overhead. We present a runtime+compiler framework to tie hardware performance counter information to a dynamic compiler and argue that the overhead is low and fine-grained. As parallel architectures or multi-core architectures proliferate, performance issues will play a crucial role in all compilation engines, and our paper reports on a modular approach to make such counter information available to the compiler.