Streaming implementation of a sequential decompression algorithm on an FPGA
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
FPGA Accelerated Low-Latency Market Data Feed Processing
HOTI '09 Proceedings of the 2009 17th IEEE Symposium on High Performance Interconnects
Efficient event processing through reconfigurable hardware for algorithmic trading
Proceedings of the VLDB Endowment
High Frequency Trading Acceleration Using FPGAs
FPL '11 Proceedings of the 2011 21st International Conference on Field Programmable Logic and Applications
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In High Frequency Trading systems, a large number of orders needs to be processed with minimal latency at very high data rates. We propose an FPGA based accelerator for High Frequency Trading that is able to decrease latency by an order of magnitude and increase the data rate by the same rate compared to software based CPU approaches. In particular, we focus on the acceleration of FAST, the most commonly used protocol for distributing pricing information of stock and options over the network. As FPGAs are hard to program, we present a novel Domain Specific Language that enables our engine to be programmed via software. The code is compiled by our own compiler into binary microcode that is then executed on a microcode engine. In this paper we provide detailed insights into our hardware structure and the optimizations we applied to increase the data rate and the overall processing performance.