Taking advantage of the SHECS-Based critical sections in the shared memory parallel architectures

Authors:
Tomasz Madajczak
Affiliations:
Faculty of Electronic, Telecommunication and Informatics, Dep. of Computer Systems Architectures, Gdansk University of Technology, Gdansk, Poland
Venue:
PPAM'05 Proceedings of the 6th international conference on Parallel Processing and Applied Mathematics
Year:
2005

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Abstract

This document presents a new method for implementing critical sections in the shared memory parallel architectures such as multithreaded multiprocessors integrated on a die. The method bases on Shared Explicit Cache System (SHECS) implemented in the multiprocessor. The document presents the concept of system architecture equipped with SHECS, the algorithm to implement operating system or application level locking service, and the results obtained with the method simulation on the network processor Intel IXP2800.