Token coherence: decoupling performance and correctness
Proceedings of the 30th annual international symposium on Computer architecture
Micro-architecture techniques in the intel® E8870 scalable memory controller
WMPI '04 Proceedings of the 3rd workshop on Memory performance issues: in conjunction with the 31st international symposium on computer architecture
Subspace snooping: filtering snoops with operating system support
Proceedings of the 19th international conference on Parallel architectures and compilation techniques
Taking advantage of the SHECS-Based critical sections in the shared memory parallel architectures
PPAM'05 Proceedings of the 6th international conference on Parallel Processing and Applied Mathematics
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The Scalability Port (SP) is a point-to-point cache consistent interface to build scalable shared memory multiprocessors. The SP interface consists of three layers of abstraction: the Physical Layer, the Link Layer and the Protocol Layer. The Physical Layer uses pin-efficient simultaneous bi-directional signaling and operates at 800 MHz in each direction. The Link Layer supports virtual channels and provides flow control and reliable transmission. The Protocol Layer implements cache consistency, TLB consistency, synchronization, and interrupt delivery functions among others. The first implementation of the SP interface is in the Intel® E8870 and E9870 chipset for the Intel Itanium® 2 processor and future generations of the Itanium processor family [1].