Static scheduling of conditional branches in parallel programs
Journal of Parallel and Distributed Computing
Edge profiling versus path profiling: the showdown
POPL '98 Proceedings of the 25th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Run-time voltage hopping for low-power real-time systems
Proceedings of the 37th Annual Design Automation Conference
Real-time dynamic voltage scaling for low-power embedded operating systems
SOSP '01 Proceedings of the eighteenth ACM symposium on Operating systems principles
Intra-Task Voltage Scheduling for Low-Energy, Hard Real-Time Applications
IEEE Design & Test
Profile-based optimal intra-task voltage scheduling for hard real-time applications
Proceedings of the 41st annual Design Automation Conference
An intra-task DVS algorithm exploiting path probabilities for real-time systems
ACM SIGBED Review - Special issue: IEEE RTAS 2005 work-in-progress
Intra-task voltage scheduling on DVS-enabled hard real-time systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In this paper, we present a novel intra-task Dynamic Voltage Scheduling (DVS) algorithm based on the knowledge of frequently executed paths in the control flow graph for real-time embedded systems. The basic idea is to construct a common path composing all the frequently executed paths (hot-paths) and perform DVS scheduling based on this common path, rather than the most probable path. We compare the performance (energy consumption) of our algorithm with a recently proposed algorithm. Our simulation results show that the proposed algorithm performs better than the existing algorithm for most of the simulated conditions. We also identify interesting research problems in this context.