Artificial neural network engine: parallel and parameterized architecture implemented in FPGA

Authors:
Milene Barbosa Carvalho;Alexandre Marques Amaral;Luiz Eduardo da Silva Ramos;Carlos Augusto Paiva da Silva Martins;Petr Ekel
Affiliations:
Pontifical Catholic University of Minas Gerais, Brazil;Pontifical Catholic University of Minas Gerais, Brazil;Pontifical Catholic University of Minas Gerais, Brazil;Pontifical Catholic University of Minas Gerais, Brazil;Pontifical Catholic University of Minas Gerais, Brazil
Venue:
PReMI'05 Proceedings of the First international conference on Pattern Recognition and Machine Intelligence
Year:
2005

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Guest editorial - Special issue on neural networks hardware implementations

IEEE Transactions on Neural Networks

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Abstract

In this paper we present and analyze an artificial neural network hardware engine, its architecture and implementation. The engine was designed to solve performance problems of the serial software implementations. It is based on a hierarchical parallel and parameterized architecture. Taking into account verification results, we conclude that this engine improves the computational performance, producing speedups from 52.3 to 204.5 and its architectural parameterization provides more flexibility.