Extensional equivalence for transition systems
Acta Informatica
Algebraic theory of processes
Theoretical Computer Science
A Testing Theory for LOTOS using Deadlock Detection
Proceedings of the IFIP WG6.1 Ninth International Symposium on Protocol Specification, Testing and Verification IX
Formal Test Automation: A Simple Experiment
Proceedings of the IFIP TC6 12th International Workshop on Testing Communicating Systems: Method and Applications
FM'05 Proceedings of the 2005 international conference on Formal Methods
Test generation based on symbolic specifications
FATES'04 Proceedings of the 4th international conference on Formal Approaches to Software Testing
A test generation framework for quiescent real-time systems
FATES'04 Proceedings of the 4th international conference on Formal Approaches to Software Testing
Online testing of real-time systems using UPPAAL
FATES'04 Proceedings of the 4th international conference on Formal Approaches to Software Testing
Formal testing from timed finite state machines
Computer Networks: The International Journal of Computer and Telecommunications Networking
TestCom '08 / FATES '08 Proceedings of the 20th IFIP TC 6/WG 6.1 international conference on Testing of Software and Communicating Systems: 8th International Workshop
Formal testing of systems presenting soft and hard deadlines
FSEN'07 Proceedings of the 2007 international conference on Fundamentals of software engineering
Testing finite state machines presenting stochastic time and timeouts
EPEW'07 Proceedings of the 4th European performance engineering conference on Formal methods and stochastic models for performance evaluation
Testing timed systems modeled by Stream X-machines
Software and Systems Modeling (SoSyM)
Implementing conformiq Qtronic
TestCom'07/FATES'07 Proceedings of the 19th IFIP TC6/WG6.1 international conference, and 7th international conference on Testing of Software and Communicating Systems
A formal framework to test soft and hard deadlines in timed systems
Software Testing, Verification & Reliability
Testing with inputs and outputs in CSP
FASE'13 Proceedings of the 16th international conference on Fundamental Approaches to Software Engineering
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In formal testing, the assumption of input enabling is typically made. This assumption requires all inputs to be enabled anytime. In addition, the useful concept of quiescence is sometimes applied. Briefly, a system is in a quiescent state when it cannot produce outputs. In this paper, we relax the input enabling assumption, and allow some input sets to be enabled while others remain disabled. Moreover, we also relax the general bound M used in timed systems to detect quiescence, and allow different bounds for different sets of outputs. By considering the tiocoM theory, an enriched theory for timed testing with repetitive quiescence, and allowing the partition of input sets and output sets, we introduce the mtioco$_{\mathcal{M}}$ relation. A test derivation procedure which is nondeterministic and parameterized is further developed, and shown to be sound and complete wrt mtioco$_{\mathcal{M}}$.