Implementing the elliptic curve method of factoring in reconfigurable hardware

Authors:
Kris Gaj;Soonhak Kwon;Patrick Baier;Paul Kohlbrenner;Hoang Le;Mohammed Khaleeluddin;Ramakrishna Bachimanchi
Affiliations:
Dept. of Electrical and Computer Engineering, George Mason University, Fairfax, Virginia;Inst. of Basic Science, Sungkyunkwan University, Suwon, Korea;Dept. of Electrical and Computer Engineering, George Mason University, Fairfax, Virginia;Dept. of Electrical and Computer Engineering, George Mason University, Fairfax, Virginia;Dept. of Electrical and Computer Engineering, George Mason University, Fairfax, Virginia;Dept. of Electrical and Computer Engineering, George Mason University, Fairfax, Virginia;Dept. of Electrical and Computer Engineering, George Mason University, Fairfax, Virginia
Venue:
CHES'06 Proceedings of the 8th international conference on Cryptographic Hardware and Embedded Systems
Year:
2006

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Abstract

A novel portable hardware architecture for the Elliptic Curve Method of factoring, designed and optimized for application in the relation collection step of the Number Field Sieve, is described and analyzed. A comparison with an earlier proof-of-concept design by Pelzl, Šimka, et al. has been performed, and a substantial improvement has been demonstrated in terms of both the execution time and the area-time product. The ECM architecture has been ported across three different families of FPGA devices in order to select the family with the best performance to cost ratio. A timing comparison with a highly optimized software implementation, GMP-ECM, has been performed. Our results indicate that low-cost families of FPGAs, such as Xilinx Spartan 3, offer at least an order of magnitude improvement over the same generation of microprocessors in terms of the performance to cost ratio.