Lattice sieving and trial division
ANTS-I Proceedings of the First International Symposium on Algorithmic Number Theory
Attacking elliptic curve cryptosystems with special-purpose hardware
Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays
Special-Purpose Hardware in Cryptanalysis: The Case of 1,024-Bit RSA
IEEE Security and Privacy
Special-Purpose Hardware for Solving the Elliptic Curve Discrete Logarithm Problem
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Non-wafer-Scale Sieving Hardware for the NFS: Another Attempt to Cope with 1024-Bit
EUROCRYPT '07 Proceedings of the 26th annual international conference on Advances in Cryptology
CAIRN 2: An FPGA Implementation of the Sieving Step in the Number Field Sieve Method
CHES '07 Proceedings of the 9th international workshop on Cryptographic Hardware and Embedded Systems
EUROCRYPT '09 Proceedings of the 28th Annual International Conference on Advances in Cryptology: the Theory and Applications of Cryptographic Techniques
PET SNAKE: a special purpose architecture to implement an algebraic attack in hardware
Transactions on computational science X
Implementing the elliptic curve method of factoring in reconfigurable hardware
CHES'06 Proceedings of the 8th international conference on Cryptographic Hardware and Embedded Systems
A simpler sieving device: combining ECM and TWIRL
ICISC'06 Proceedings of the 9th international conference on Information Security and Cryptology
Analysis on the clockwise transposition routing for dedicated factoring devices
WISA'05 Proceedings of the 6th international conference on Information Security Applications
A tutorial on high performance computing applied to cryptanalysis
EUROCRYPT'12 Proceedings of the 31st Annual international conference on Theory and Applications of Cryptographic Techniques
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Since 1999 specialized hardware architectures for factoring numbers of 1024 bit size with the General Number Field Sieve (GNFS) have attracted a lot of attention ([Ber], [ST]). Concerns about the feasibility of giant monolytic ASIC architectures such as TWIRL have been raised. Therefore, we propose a parallelized lattice sieving device called SHARK, which completes the sieving step of the GNFS for a 1024-bit number in one year. Its architecture is modular and consists of small ASICs connected by a specialized butterfly transport system. We estimate the costs of such a device to be less than US$ 200 million. Because of the modular architecture based on small ASICs, we claim that this device can be built with today's technology.