Two-level adaptive training branch prediction
MICRO 24 Proceedings of the 24th annual international symposium on Microarchitecture
Dynamic history-length fitting: a third level of adaptivity for branch prediction
Proceedings of the 25th annual international symposium on Computer architecture
Variable length path branch prediction
Proceedings of the eighth international conference on Architectural support for programming languages and operating systems
ARM System-on-Chip Architecture
ARM System-on-Chip Architecture
Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
Elastic History Buffer: A Low-Cost Method to Improve Branch Prediction Accuracy
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
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The branch prediction accuracy is one of essential parts of performance improvement in embedded processors as well as modern microarchitectures. Until now, the length of branch history has been statically fixed for all branch instructions, and the history length is usually selected in accordance with the size of prediction table. In this paper, we propose a dynamic per-branch history length adjustment policy, which can dynamically change the history length for each branch instruction. The proposed solution tracks data dependencies of branch instructions and identifies strongly correlated branches in branch history. Compared to the previous bimodal style predictors and the fixed history length predictors in embedded processors, our method provides better history length for each branch instruction, resulting in substantial improvement in prediction accuracy.