A novel low voltage very low power CMOS class AB current output stage with ultra high output current drive capability

• Authors: Leila Safari;Seyed Javad Azhari
• Venue: Microelectronics Journal
• Year: 2012

In this paper a novel low voltage (LV) very low power (VLP) class AB current output stage (COS) with extremely high linearity and high output impedance is presented. A novel current splitting method is used to minimize the transistors gate-source voltages providing LV operation and ultra high current drive capability. High linearity and very high output impedance are achieved employing a novel resistor based current mirror avoiding conventional cascode structures to be used. The operation of the proposed COS has been verified through HSPICE simulations based on TSMC 0.18@mm CMOS technology parameters. Under supply voltage of +/-0.7V and bias current of 5@mA, it can deliver output currents as high as 14mA with THD better than -53dB and extremely high output impedance of 320M@W while consuming only 29@mW. This makes the proposed COS to have ultra large current drive ratio (I"o"u"t"m"a"x/I"b"i"a"s or the ratio of peak output current to the bias current of output branch transistors) of 2800. By increasing supply voltage to +/-0.9V, it can deliver extremely large output current of +/-24mA corresponding to 3200 current drive ratio while consuming only 42.9@mW and exhibiting high output impedance of 350M@W. Interestingly, the proposed COS is the first yet reported one with such extremely high output current and a THD even less than -45dB. Such ultra high current drive capability, high linearity and high output impedance make the proposed COS an outstanding choice for LV, VLP and high drive current mode circuits. The superiority of the proposed COS gets more significance by showing in this work that conventional COS can deliver only +/-3.29mA in equal condition. The proposed COS also exhibits high positive and negative power supply rejection ratio (PSRR+/PSRR-) of 125dB and 130dB, respectively. That makes it very suitable for LV, VLP mixed mode applications. The Monte Carlo simulation results are provided, which prove the outstanding robust performance of the proposed block versus process tolerances. Favorably the proposed COS resolves the major limitation of current output stages that so far has prevented designing high drive current mode circuits under low supply voltages. In brief, the deliberate combination of so many effective novel methods presents a wonderful phenomenal COS block to the world of science and engineering.