A low-voltage low-power CMOS fully differential linear transconductor with mobility reduction compensation

Authors:
Tamer Farouk;Ahmed Nader Mohieldin;Ahmed Hussien Khalil
Affiliations:
Department of Electrical Engineering, Cairo University, Giza 12613, Egypt;Department of Electrical Engineering, Cairo University, Giza 12613, Egypt;Department of Electrical Engineering, Cairo University, Giza 12613, Egypt
Venue:
Microelectronics Journal
Year:
2012

Citing 2
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Abstract

A highly linear fully differential CMOS transconductor architecture based on flipped voltage follower (FVF) is proposed. The linearity of the proposed architecture is improved by mobility reduction compensation technique. The simulated total harmonic distortion (THD) of the proposed transconductor with 0.4V"p"p differential input is improved from -42dB to -55dB while operating from 1.0V supply. As an example of the applications of the proposed transconductor, a 4th-order 5MHz Butterworth Gm-C filter is presented. The filter has been designed and simulated in UMC 130nm CMOS process. It achieves THD of -53dB for 0.4V"p"p differential input. It consumes 345@mw from 1.0V single supply. Theoretical and simulated results are in good agreement.