Toward real time fractal image compression using graphics hardware

Authors:
Ugo Erra
Affiliations:
ISISLab – Dipartimento di Informatica ed Appl. “R.M. Capocelli”, Università degli Studi di Salerno, Baronissi, Italy
Venue:
ISVC'05 Proceedings of the First international conference on Advances in Visual Computing
Year:
2005

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Abstract

In this paper, we present a parallel fractal image compression using the programmable graphics hardware. The main problem of fractal compression is the very high computing time needed to encode images. Our implementation exploits SIMD architecture and inherent parallelism of recently graphic boards to speed-up baseline approach of fractal encoding. The results we present are achieved on cheap and widely available graphics boards.