eNVy: a non-volatile, main memory storage system
ASPLOS VI Proceedings of the sixth international conference on Architectural support for programming languages and operating systems
Cleaning policies in mobile computers using flash memory
Journal of Systems and Software
An Adaptive Striping Architecture for Flash Memory Storage Systems of Embedded Systems
RTAS '02 Proceedings of the Eighth IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS'02)
An efficient management scheme for large-scale flash-memory storage systems
Proceedings of the 2004 ACM symposium on Applied computing
Storage alternatives for mobile computers
OSDI '94 Proceedings of the 1st USENIX conference on Operating Systems Design and Implementation
LSTAFF: system software for large block flash memory
AsiaSim'04 Proceedings of the Third Asian simulation conference on Systems Modeling and Simulation: theory and applications
A space-efficient flash translation layer for CompactFlash systems
IEEE Transactions on Consumer Electronics
A flash compression layer for SmartMedia card systems
IEEE Transactions on Consumer Electronics
Page replacement algorithms for NAND flash memory storages
ICCSA'07 Proceedings of the 2007 international conference on Computational science and its applications - Volume Part I
An intelligent garbage collection algorithm for flash memory storages
ICCSA'06 Proceedings of the 6th international conference on Computational Science and Its Applications - Volume Part I
CATA: a garbage collection scheme for flash memory file systems
UIC'06 Proceedings of the Third international conference on Ubiquitous Intelligence and Computing
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Flash Translation Layer (FTL) is the device driver software that makes flash memory device appear to the system like a disk drive. Since flash memory cannot be written over existing data unless erased in advance, the FTL usually employs special address mapping algorithms to avoid having to erase on every data update. In this paper, we propose a new FTL algorithm which considers the access patterns of data blocks. Proposed scheme monitors write access patterns of data blocks and intelligently manages the address mapping to improve the performance. Simulation results show that the proposed scheme improves the space utilization without significant write/update performance degradation.