ARCc: A case for an architecturally redundant cache-coherence architecture for large multicores

Authors:
Omer Khan;Henry Hoffmann;Mieszko Lis;Farrukh Hijaz;Anant Agarwal;Srinivas Devadas
Affiliations:
University of Massachusetts, Lowell, USA;Massachusetts Institute of Technology, Cambridge, USA;Massachusetts Institute of Technology, Cambridge, USA;University of Massachusetts, Lowell, USA;Massachusetts Institute of Technology, Cambridge, USA;Massachusetts Institute of Technology, Cambridge, USA
Venue:
ICCD '11 Proceedings of the 2011 IEEE 29th International Conference on Computer Design
Year:
2011

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Abstract

This paper proposes an architecturally redundant cache-coherence architecture (ARCc) that combines the directory and shared-NUCA based coherence protocols to improve performance, energy and dependability. Both coherence mechanisms co-exist in the hardware and ARCc enables seamless transition between the two protocols. We present an online analytical model implemented in the hardware that predicts performance and triggers a transition between the two coherence protocols at application-level granularity. The ARCc architecture delivers up to 1.6脳 higher performance and up to 1.5脳 lower energy consumption compared to the directory-based counterpart. It does so by identifying applications which benefit from the large shared cache capacity of shared-NUCA because of lower off-chip accesses, or where remote-cache word accesses are efficient.