Performance evaluation of the parallel packet switch with a sliding window scheme

  • Authors:
  • Chia-Lung Liu;Chiou Moh;Chin-Chi Wu;Woei Lin

  • Affiliations:
  • Department of Computer Science, National Chung-Hsing University, Taichung, Taiwan;Nan Kai Institute of Technology;Nan Kai Institute of Technology;Department of Computer Science, National Chung-Hsing University, Taichung, Taiwan

  • Venue:
  • ICCSA'06 Proceedings of the 2006 international conference on Computational Science and Its Applications - Volume Part II
  • Year:
  • 2006

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Abstract

This study analyzes how parallel packet switching (PPS) performs with a sliding window (SW). The PPS involves numerous packet switches that operate independently and in parallel. The typical PPS dispatch algorithm applies a round-robin method (RR). The class of PPS is characterized by deploying parallel center-stage switches that enable all memory buffers run more slowly than the external line rate. A novel SW packet switching method for PPS, called SW-PPS, is developed. The SW-PPS operates in a pipeline fashion to ensure overall switching. The performance of the RR-PPS and SW-PPS is evaluated for a torus topology. Under identical Bernoulli, the SW-PPS provided considerably outperformed RR-PPS. Furthermore, this investigation proposes a mathematical analytical model for RR-PPS and SW-PPS.