Parallel Packet Switching Using Multiplexors with Virtual Input Queues
LCN '02 Proceedings of the 27th Annual IEEE Conference on Local Computer Networks
Analysis of the parallel packet switch architecture
IEEE/ACM Transactions on Networking (TON)
Matching output queueing with a combined input/output-queued switch
IEEE Journal on Selected Areas in Communications
IEEE Journal on Selected Areas in Communications
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This study analyzes how parallel packet switching (PPS) performs with a sliding window (SW). The PPS involves numerous packet switches that operate independently and in parallel. The typical PPS dispatch algorithm applies a round-robin method (RR). The class of PPS is characterized by deploying parallel center-stage switches that enable all memory buffers run more slowly than the external line rate. A novel SW packet switching method for PPS, called SW-PPS, is developed. The SW-PPS operates in a pipeline fashion to ensure overall switching. The performance of the RR-PPS and SW-PPS is evaluated for a torus topology. Under identical Bernoulli, the SW-PPS provided considerably outperformed RR-PPS. Furthermore, this investigation proposes a mathematical analytical model for RR-PPS and SW-PPS.