An evolutionary management scheme in high-performance packet switches
IEEE/ACM Transactions on Networking (TON)
Journal of Electrical and Computer Engineering
Performance evaluation of the parallel packet switch with a sliding window scheme
ICCSA'06 Proceedings of the 2006 international conference on Computational Science and Its Applications - Volume Part II
Effect of unbalanced bursty traffic on memory-sharing schemes for internet switching architecture
ICN'05 Proceedings of the 4th international conference on Networking - Volume Part I
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Shared-memory based packet switches are known to provide the best possible throughput performance for bursty data traffic in high-speed packet networks and internets compared with other buffering strategies under conditions of identical memory resources deployed in the switch. However, scaling of shared-memory packet switches to a larger size has been restricted mainly due to the physical limitations imposed by the memory-access speed and the centralized control for switching functions in shared-memory switches. A new scalable architecture for a shared-memory packet switch, called the sliding-window (SW) switch, is proposed to overcome these limitations. The SW switch introduces a new class of switching architecture, where physically separate multiple memory modules are logically shared among all the ports of the switch, and the control is decentralized. The SW switch alleviates the bottleneck caused by the centralized control of switching functions in large shared-memory switches. Decentralized switching functions enable the SW switch to operate in a pipeline fashion to enhance scalability and switching capacity compared with that of previously known classes of shared-memory switch architecture.