Architecture-aware custom instruction generation for reconfigurable processors

Authors:
Alok Prakash;Siew-Kei Lam;Amit Kumar Singh;Thambipillai Srikanthan
Affiliations:
Center for High Performance Embedded Systems, School of Computer Engineering, Nanyang Technological University;Center for High Performance Embedded Systems, School of Computer Engineering, Nanyang Technological University;Center for High Performance Embedded Systems, School of Computer Engineering, Nanyang Technological University;Center for High Performance Embedded Systems, School of Computer Engineering, Nanyang Technological University
Venue:
ARC'10 Proceedings of the 6th international conference on Reconfigurable Computing: architectures, Tools and Applications
Year:
2010

Citing 7
Cited 0

Automatic application-specific instruction-set extensions under microarchitectural constraints

Proceedings of the 40th annual Design Automation Conference
A graph covering algorithm for a coarse grain reconfigurable system

Proceedings of the 2003 ACM SIGPLAN conference on Language, compiler, and tool for embedded systems
Application-specific instruction generation for configurable processor architectures

FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Automated Custom Instruction Generation for Domain-Specific Processor Acceleration

IEEE Transactions on Computers
Rapid design of area-efficient custom instructions for reconfigurable embedded processing

Journal of Systems Architecture: the EUROMICRO Journal
Recurrence-aware instruction set selection for extensible embedded processors

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fast Identification of Custom Instructions for Extensible Processors

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

Instruction set extension is becoming extremely popular for meeting the tight design constraints in embedded systems. This mechanism is now widely supported by commercially available FPGA (Field-Programmable Gate Array) based reconfigurable processors. In this paper, we present a design flow that automatically enumerates and selects custom instructions from an application DFG (Data-Flow Graph) in an architecture-aware manner. Unlike previously reported methods, the proposed enumeration approach identifies custom instruction patterns that can be mapped onto the target FPGA in a predictable manner. Our investigation shows that using this strategy the selection process can make a more informed decision for selecting a set of custom instructions that will lead to higher performance at lower cost. Experimental results based on six applications from a widely-used benchmark suite show that the proposed design flow can achieve significantly higher performance gain when compared to conventional design approaches.