Introduction To Automata Theory, Languages, And Computation
Introduction To Automata Theory, Languages, And Computation
Asim: A Performance Model Framework
Computer
Assisting Network Intrusion Detection with Reconfigurable Hardware
FCCM '02 Proceedings of the 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Implementation of a Content-Scanning Module for an Internet Firewall
FCCM '03 Proceedings of the 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Deep Packet Filter with Dedicated Logic and Read Only Memories
FCCM '04 Proceedings of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Scalable Pattern Matching for High Speed Networks
FCCM '04 Proceedings of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Fast Regular Expression Matching Using FPGAs
FCCM '01 Proceedings of the the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
A Scalable Architecture For High-Throughput Regular-Expression Pattern Matching
Proceedings of the 33rd annual international symposium on Computer Architecture
Algorithms to accelerate multiple regular expressions matching for deep packet inspection
Proceedings of the 2006 conference on Applications, technologies, architectures, and protocols for computer communications
Compiling PCRE to FPGA for accelerating SNORT IDS
Proceedings of the 3rd ACM/IEEE Symposium on Architecture for networking and communications systems
Regular Expression Matching in Reconfigurable Hardware
Journal of Signal Processing Systems
Optimization of pattern matching circuits for regular expression on FPGA
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Regular Expression (RE) is widely used in many aspects due to its high expressiveness, flexibility and compactness, which requires a high-performance and efficient matching method. A novel approach to accelerate RE pattern matching based on Pattern-Unit (PUREM) is proposed here, in which Pattern-Unit matching is accomplished by a Reconfigurable Function Unit (RFU). The RFU can be integrated into the pipeline of CPU architecture and shares matching jobs with software, without wrecking the compatibility of applications. Compared with other works, our approach offers a flexible mechanism under which hardware does NOT need to vary with RE patterns, and it holds the scalability that can be easily extended to most RE applications and software. For validation, the PUREM HW/SW system has been implemented on the Snort v2.8 and PCRE v7.6 applications. The experimental results show a significant speedup of 3~4x compared to the software performance on a 2GHz Pentium IV machine, where our RFU logic mapped onto Xilinx Virtex-5 XC5VLX50 only takes up 17% resource.