Static analysis by abstract interpretation of the quasi-synchronous composition of synchronous programs

Authors:
Julien Bertrane
Affiliations:
Computer Science Department, École normale supérieure, Paris, France
Venue:
VMCAI'05 Proceedings of the 6th international conference on Verification, Model Checking, and Abstract Interpretation
Year:
2005

Citing 8
Cited 2

LUSTRE: a declarative language for real-time programming

POPL '87 Proceedings of the 14th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
Abstract interpretation and application to logic programs

Journal of Logic Programming
Abstract interpretation: a unified lattice model for static analysis of programs by construction or approximation of fixpoints

POPL '77 Proceedings of the 4th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
Comparing the Galois Connection and Widening/Narrowing Approaches to Abstract Interpretation

PLILP '92 Proceedings of the 4th International Symposium on Programming Language Implementation and Logic Programming
A Protocol for Loosely Time-Triggered Architectures

EMSOFT '02 Proceedings of the Second International Conference on Embedded Software
Threshold and Bounded-Delay Voting in Critical Control Systems

FTRTFT '00 Proceedings of the 6th International Symposium on Formal Techniques in Real-Time and Fault-Tolerant Systems
A static analyzer for large safety-critical software

PLDI '03 Proceedings of the ACM SIGPLAN 2003 conference on Programming language design and implementation
Design and implementation of a special-purpose static program analyzer for safety-critical real-time embedded software

The essence of computation

Abstract interpretation of the physical inputs of embedded programs

VMCAI'08 Proceedings of the 9th international conference on Verification, model checking, and abstract interpretation
Proving the properties of communicating imperfectly-clocked synchronous systems

SAS'06 Proceedings of the 13th international conference on Static Analysis

Quantified Score

Hi-index	0.00

Visualization

Abstract

We present a framework to graphically describe and analyze embedded systems which are built on asynchronously wired synchronous subsystems. Our syntax is close to electronic diagrams. In particular, it uses logic and arithmetic gates, connected by wires, and models synchronous subsystems as boxes containing these gates. In our approach, we introduce a continuous-time semantics, connecting each point of the diagram to a value, at any moment. We then describe an analysis derived from the abstract interpretation framework enabling to statically and automatically prove temporal properties of the diagrams we defined. We can prove, for example, that the output of a diagram cannot be equal to a given value in a given interval of time.