Proceedings of the joint conference on Languages, compilers and tools for embedded systems: software and compilers for embedded systems
Bandwidth-Constrained Mapping of Cores onto NoC Architectures
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Flattened Butterfly Topology for On-Chip Networks
Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture
Area and power consumption estimations at system level with SystemQ 2.0
Proceedings of the 2nd International Conference on Simulation Tools and Techniques
User-centric design space exploration for heterogeneous network-on-chip platforms
Proceedings of the Conference on Design, Automation and Test in Europe
A fast and elitist multiobjective genetic algorithm: NSGA-II
IEEE Transactions on Evolutionary Computation
Transaction level modeling in practice: motivation and introduction
Proceedings of the International Conference on Computer-Aided Design
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System-on-Chip (SoC) has become a common design technique in the integrated circuits industry as it offers many advantages in terms of cost and performance efficiency. SoCs are increasingly complex and heterogeneous systems that are highly integrated comprising processors, caches, hardware accelerators, memories, peripherals and interconnects. Modern SoCs deploy not only simple buses but also crossbars and Networks-on-Chip (NoC) to connect dozens or even hundreds of modules. However, it is difficult to evaluate the performance of these interconnects because of their complexity. This is a potential design risk. In order to address this challenge, early design space exploration is required to find appropriate system architectures out of many candidate architectures. An appropriate interconnect architecture is a fundamental outcome of these evaluations since its latency and throughput characteristics affect the performance of all attached modules in the SoC. In this paper we show how to perform early design space exploration using our Electronic System Level (ESL) performance evaluation framework SystemQ. We use a heterogeneous Multi-Processor SoC that features a complex NoC as a central interconnect. Based on this example we show the importance of proper abstraction in order to keep simulation efforts manageable.