A convolutional neural network VLSI architecture using sorting model for reducing multiply-and-accumulation operations

Authors:
Osamu Nomura;Takashi Morie;Masakazu Matsugu;Atsushi Iwata
Affiliations:
Intelligent I/F Project, Canon Inc., Atsugi, Japan;Graduate School of Life Science and Systems Engineering, Kyushu Institute of Technology, Kitakyushu, Japan;Intelligent I/F Project, Canon Inc., Atsugi, Japan;A-R-Tec Corporation, Higashi-Hiroshima, Japan
Venue:
ICNC'05 Proceedings of the First international conference on Advances in Natural Computation - Volume Part III
Year:
2005

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Abstract

Hierarchical convolutional neural networks are a well-known robust image-recognition model. In order to apply this model to robot vision or various intelligent real-time vision systems, its VLSI implementation is essential. This paper proposes a new algorithm for reducing multiply-and-accumulation operation by sorting neuron outputs by magnitude. We also propose a VLSI architecture based on this algorithm. We have designed and fabricated a sorting LSI by using a 0.35 μm CMOS process. We have verified successful sorting operations at 100 MHz clock cycle by circuit simulation.