LSCs: Breathing Life into Message Sequence Charts
Formal Methods in System Design
Practical Formal Methods for Hardware Design
Practical Formal Methods for Hardware Design
Formal Development of Reactive Systems - Case Study Production Cell
Using a Visual Formalism for Design Verification in Industrial Environments
ACoS '98/VISUAL '98, AIN '97 Selected papers on Services and Visualization: Towards User-Friendly Design
A semantically-derived subset of English for hardware verification
ACL '99 Proceedings of the 37th annual meeting of the Association for Computational Linguistics on Computational Linguistics
The temporal logic of programs
SFCS '77 Proceedings of the 18th Annual Symposium on Foundations of Computer Science
HieroMate: a graphical tool for specification and verification of hierarchical hybrid automata
KI'09 Proceedings of the 32nd annual German conference on Advances in artificial intelligence
Modeling admissible behavior using event signals
IEEE Transactions on Systems, Man, and Cybernetics, Part B: Cybernetics
Model checking-based safety verification for railway signal safety protocol-I
International Journal of Computer Applications in Technology
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Control software of a manufacturing system is usually designed separated from the real plant or its simulation. Undesired behavior can occur after transferring software to the controller. At best, errors are recognized when starting-up, but there can exist failures that occur rarely and seemingly randomly during operation phase. This problem is of high significance, since the complexity of automated systems rises. Hence, control software bugs should be considered in early project phase. The approach presents an integrated framework that facilitates virtual start-up of a plant. It applies formal methods to simulate and even verify control software. This eases control software design and reduces plant downtimes.