Automatic verification of finite-state concurrent systems using temporal logic specifications
ACM Transactions on Programming Languages and Systems (TOPLAS)
Assisting requirement formalization by means of natural language translation
Formal Methods in System Design
Formal methods: state of the art and future directions
ACM Computing Surveys (CSUR) - Special ACM 50th-anniversary issue: strategic directions in computing research
Property specification patterns for finite-state verification
FMSP '98 Proceedings of the second workshop on Formal methods in software practice
Symbolic Model Checking
Design and Synthesis of Synchronization Skeletons Using Branching-Time Temporal Logic
Logic of Programs, Workshop
Linear vs. Branching Time: A Complexity-Theoretic Perspective
LICS '98 Proceedings of the 13th Annual IEEE Symposium on Logic in Computer Science
A unified approach to hardware verification through a heterogeneous logic of design diagrams
A unified approach to hardware verification through a heterogeneous logic of design diagrams
A Two-Variable Fragment of English
Journal of Logic, Language and Information
An Authoring Tool for Informal and Formal Requirements Specifications
FASE '02 Proceedings of the 5th International Conference on Fundamental Approaches to Software Engineering
TACAS '00 Proceedings of the 6th International Conference on Tools and Algorithms for Construction and Analysis of Systems: Held as Part of the European Joint Conferences on the Theory and Practice of Software, ETAPS 2000
Generating text with a theorem prover
Proceedings of the workshop on Student research
Real-time specification patterns
Proceedings of the 27th international conference on Software engineering
Natural Language Specification of Performance Trees
EPEW '08 Proceedings of the 5th European Performance Engineering Workshop on Computer Performance Engineering
Virtual start-up of plants using formal methods
International Journal of Computer Applications in Technology
Hi-index | 0.00 |
To verify hardware designs by model checking, circuit specifications are commonly expressed in the temporal logic CTL. Automatic conversion of English to CTL requires the definition of an appropriately restricted subset of English. We show how the limited semantic expressibility of CTL can be exploited to derive a hierarchy of subsets. Our strategy avoids potential difficulties with approaches that take existing computational semantic analyses of English as their starting point---such as the need to ensure that all sentences in the subset possess a CTL translation.