Low-Power VLSI architectures for OFDM transmitters based on PAPR reduction

Authors:
Th. Giannopoulos;Vassilis Paliouras
Affiliations:
Electrical & Computer Engineering Department, University of Patras, Patras, Greece;Electrical & Computer Engineering Department, University of Patras, Patras, Greece
Venue:
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Year:
2005

Citing 0
Cited 2

A Low-Complexity PTS-based PAPR Reduction Technique for OFDM Signals without Transmission of Side Information

Journal of Signal Processing Systems
Low-power maximum magnitude computation for PAPR reduction in OFDM transmitters

PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation

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Abstract

This paper introduces a quantitative approach to the reduction of system-level power dissipation reducing the Peak-to-Average Power Ratio (PAPR) in multicarrier systems. In particular introduces a VLSI implementation of Partial Transmit Sequences (PTS) approach. PTS is a distortionless Peak-to-Average Power Ratio (PAPR) reduction scheme suitable for Orthogonal Frequency Division Multiplexing (OFDM) which imposes low additional complexity to the overall system. We show that the application of this method reduces the power consumption of the complete digital-analog system by even 12.6%. Furthermore, this paper examines theoretically the relationship between the achieved PAPR reduction and the corresponding PA efficiency. Subsequently the achieved PAPR reduction and the corresponding power saving are evaluated via simulation.