RF microelectronics
Low-Power VLSI architectures for OFDM transmitters based on PAPR reduction
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Journal of Signal Processing Systems
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Increased Peak-to-Average Power Ratio (PAPR) is a serious drawback in an Orthogonal Frequency Division Multiplexing (OFDM) system, leading to inefficient amplification of the transmitted signal. Partial Transmit Sequences (PTS) approach is a distortionless PAPR-reduction scheme which imposes low additional complexity to the overall system. This paper introduces a new version of the PTS algorithm which selects weighting factors from a different set than the ones commonly used. Furthermore, this paper proposes a new PAPR estimation method that reduces the implementation complexity. The proposed architecture reduces the power consumption of the complete transmitter by up to 22% in comparison to OFDM systems where no PAPR reduction method is employed, depending on the power consumption of the power amplifier.