High-level modelling, analysis, and verification on FPGA-based hardware design

Authors:
Petr Matoušek;Aleš Smrčka;Tomáš Vojnar
Affiliations:
FIT, Brno University of Technology, Brno, Czech Republic;FIT, Brno University of Technology, Brno, Czech Republic;FIT, Brno University of Technology, Brno, Czech Republic
Venue:
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
Year:
2005

Citing 1
Cited 1

TReX: A Tool for Reachability Analysis of Complex Systems

CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification

FPGA based tester tool for hybrid real-time systems

Microprocessors & Microsystems

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Abstract

The paper presents high-level modelling and formal analysis and verification on an FPGA-based multigigabit network monitoring system called Scampi. Uppaal was applied in this work to establish some correctness and throughput results on a model intentionally built using patterns reusable in other similar projects. Some initial experiments with parametric analysis using TReX were performed too.