Symbolic noise modeling, analysis and optimization of a CMOS input buffer

  • Authors:
  • Santosh Kumar Patnaik;Swapna Banerjee

  • Affiliations:
  • Department of E&ECE, IIT, Kharagpur, India;Department of E&ECE, IIT, Kharagpur, India

  • Venue:
  • Analog Integrated Circuits and Signal Processing
  • Year:
  • 2012

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Abstract

This paper presents the symbolic noise modeling, analysis and optimization of an Input Buffer designed using RFCMOS technology, intended to be used in a high speed Track and Hold Amplifier (THA). The symbolic noise modeling and analysis are carried out by modeling each RF-MOSFET present in the Input Buffer by its nullor equivalent noise model. This helps in better understanding the noise involvement with the circuit and its optimization. All the extrinsic and intrinsic components associated with the RF-MOSFET used for the symbolic noise analysis are obtained using parameter extraction technique. The parameter extraction and symbolic noise analysis are done using MATLAB. The results obtained through MATLAB simulation are in good agreement with the results obtained from SPICE.