Plasma atomic layer deposited TiN metal gate for three dimensional device applications: Deposition temperature, capping metal and post annealing

  • Authors:

  • Seung Chan Heo;Changhwan Choi

  • Affiliations:

  • Division of Materials Science and Engineering, Hanyang University, 17 Haengdang-Dong, Seongdong-Gu, Seoul 133-791, Republic of Korea;Division of Materials Science and Engineering, Hanyang University, 17 Haengdang-Dong, Seongdong-Gu, Seoul 133-791, Republic of Korea

  • Venue:
  • Microelectronic Engineering
  • Year:
  • 2012

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Abstract

We evaluated plasma atomic layer deposition (ALD)-based TiN as a gate electrode for the metal-oxide-semiconductor (MOS) devices application by varying thickness, deposition temperature, subsequent metal capping layer and post forming gas anneal (FGA). Lower deposition temperature, thinner TiN, in situ processed ALD TaN capping provides more positive flatband voltage (V"F"B), compatible for p-type MOS devices. Equivalent oxide thickness (EOT) can be scaled down to ~1.2nm range. With post 450^oC FGA, additional negative V"F"B shift is observed while EOT is substantially increased (0.2-0.3nm). Mid-gap work-function behavior is observed with plasma ALD-based TiN, indicating a strong potential candidate metal gate material for replacement gate processed three-dimensional (3-D) devices such as FiN shaped field effect transistor (FiNFET).