Delay and bus current evaluation in CMOS logic circuits
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Power estimation tool for sub-micron CMOS VLSI circuits
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Power estimation techniques for integrated circuits
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Effects of correlations on accuracy of power analysis—an experimental study
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
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Today's digital design systems are running out of steam, when it comes to meeting the challenges presented by simultaneous switching, power consumption and reliabilty constraints emerging in VLSI circuits. In this paper a new technique to accurately estimate the transient behavior of large CMOS cell-based circuits in a reasonable amount of time is presented. Gate-level simulations and a consistent modeling methodology are employed to compute the time-domain waveforms for signal voltages, supply currents, power consumption and &Dgr;&Igr; noise on power lines. This can be done for circuit blocks and complete designs by our new tool POWTIM, which adds SPICE-like capabilities to digital design standards.