Practical methods of optimization; (2nd ed.)
Practical methods of optimization; (2nd ed.)
Performance-constrained worst-case variability minimization of VLSI circuits
DAC '93 Proceedings of the 30th international Design Automation Conference
Synthesis of high-performance analog cells in ASTRX/OBLX
Synthesis of high-performance analog cells in ASTRX/OBLX
ASTRX/OBLX: tools for rapid synthesis of high-performance analog circuits
DAC '94 Proceedings of the 31st annual Design Automation Conference
Performance of a new annealing schedule
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Synthesis tools for mixed-signal ICs: progress on frontend and backend strategies
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Structured design of microelectromechanical systems
DAC '97 Proceedings of the 34th annual Design Automation Conference
MAELSTROM: efficient simulation-based synthesis for custom analog cells
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Synthesis of analog and mixed-signal integrated electronic circuits
Formal engineering design synthesis
Layout-Aware RF Circuit Synthesis Driven by Worst Case Parasitic Corners
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
ASLIC: a low power CMOS analog circuit design automation
Integration, the VLSI Journal
ASLIC: A low power CMOS analog circuit design automation
Integration, the VLSI Journal
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We describe a synthesis system that takes operating range constraints and inter- and intra-circuit parametric manufacturing variations into account while designing a sized and biased analog circuit. Previous approaches to CAD for analog circuit synthesis have concentrated on nominal analog circuit design, and subsequent optimization of these circuits for statistical fluctuations and operating point ranges. Our approach simultaneously synthesizes and optimizes for operating and manufacturing variations by mapping the circuit design problem into an Infinite Programming problem and solving it using an annealing within annealing formulation. We present circuits designed by this integrated synthesis system, and show that they indeed meet their operating range and parametric manufacturing constraints.