Combinatorial optimization: algorithms and complexity
Combinatorial optimization: algorithms and complexity
The temporal logic of reactive and concurrent systems
The temporal logic of reactive and concurrent systems
Using integer programming to verify general safety and liveness properties
Formal Methods in System Design - Special issue on computer-aided verification (based on CAV'92 workshop)
On Communicating Finite-State Machines
Journal of the ACM (JACM)
Verification of Safety Properties Using IntegerProgramming: Beyond the State Equation
Formal Methods in System Design
Improving the Precision of INCA by Eliminating Solutions with Spurious Cycles
IEEE Transactions on Software Engineering
Software Verification Based on Linear Programming
FM '99 Proceedings of the Wold Congress on Formal Methods in the Development of Computing Systems-Volume II
Model Checking LTL Using Constraint Programming
ICATPN '97 Proceedings of the 18th International Conference on Application and Theory of Petri Nets
Software Model Checking: The VeriSoft Approach
Formal Methods in System Design
Spin model checker, the: primer and reference manual
Spin model checker, the: primer and reference manual
Counterexample-based refinement for a boundedness test for CFSM languages
SPIN'05 Proceedings of the 12th international conference on Model Checking Software
A region graph based approach to termination proofs
TACAS'06 Proceedings of the 12th international conference on Tools and Algorithms for the Construction and Analysis of Systems
Dependency Analysis for Control Flow Cycles in Reactive Communicating Processes
SPIN '08 Proceedings of the 15th international workshop on Model Checking Software
Static detection of Livelocks in Ada multitasking programs
Ada-Europe'07 Proceedings of the 12th international conference on Reliable software technologies
Static livelock analysis in CSP
CONCUR'11 Proceedings of the 22nd international conference on Concurrency theory
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We describe an incomplete but sound and efficient livelock freedom test for infinite state asynchronous reactive systems. The method abstracts a system into a set of simple control flow cycles labeled with their message passing effects. From these cycles, it constructs a homogeneous integer programming problem (IP) encoding a necessary condition for the existence of livelock runs. Livelock freedom is assured by the infeasibility of the generated homogeneous IP, which can be checked in polynomial time. In the case that livelock freedom cannot be proved, the method proposes a counterexample given as a set of cycles. We apply an automated cycle dependency analysis to counterexamples to check their spuriousness and to refine the abstraction. We illustrate the application of the method to Promela models using our prototype implementation named aLive.