Low power and low jitter wideband clock synthesizers in CMOS ASICs

• Authors: Régis Roubadia;Sami Ajram;Guy Cathébras
• Venue: PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
• Year: 2006

This paper introduces two low power design techniques to improve both the jitter and phase noise of PLL frequency synthesizers used in ASICs. These techniques focus on the noise current reduction in wideband ring VCOs. Two PLLs embedding such VCOs were implemented, in 0.18μm and 0.13μm CMOS technologies, under 1.8V and 1.2V supply voltages respectively. The maximum improvement was observed for a 1.8V PLL running at 160MHz and consuming 1.6mW, which phase noise was reduced from -81.4dBc/Hz to -88.4dBc/Hz.