Static and dynamic power reduction by architecture selection

Authors:
Christian Piguet;Christian Schuster;Jean-Luc Nagel
Affiliations:
CSEM Centre Suisse d'Electronique et de Microtechnique, Neuchâtel, Switzerland;IMT Institut de Microtechnique, University of Neuchâtel, Neuchâtel, Switzerland;CSEM Centre Suisse d'Electronique et de Microtechnique, Neuchâtel, Switzerland
Venue:
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Year:
2006

Citing 2
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Abstract

As leakage power and total power is a more and more dramatic issue in very deep submicron technologies, this paper explores new design methodologies for designing leakage tolerant digital architectures, based on architectural parameters like activity, logical depth, number of transitions for achieving a given task and total number of gates. Various architectures for a same logic function are compared at very low Vdd and Vth that define the optimal total power consumption of each architecture. The first proposed design method selects the best architecture out of a set of architectures (baseline, sequential, parallel, pipelined, etc..) at optimal Vdd and threshold voltages Vth, while a second design method takes Vdd and threshold voltages Vth as given constraints.