FPGA implementation of an OFDM-based WLAN receiver

Authors:
María José Canet;Javier Valls;Vicenç Almenar;José Marín-Roig
Affiliations:
Instituto de Telecomunicaciones y Aplicaciones Multimedia, Universidad Politécnica de Valencia, Ctra. Nazaret-Oliva s/n, 46730 Gandia, Spain;Instituto de Telecomunicaciones y Aplicaciones Multimedia, Universidad Politécnica de Valencia, Ctra. Nazaret-Oliva s/n, 46730 Gandia, Spain;Instituto de Telecomunicaciones y Aplicaciones Multimedia, Universidad Politécnica de Valencia, Ctra. Nazaret-Oliva s/n, 46730 Gandia, Spain;Instituto de Telecomunicaciones y Aplicaciones Multimedia, Universidad Politécnica de Valencia, Ctra. Nazaret-Oliva s/n, 46730 Gandia, Spain
Venue:
Microprocessors & Microsystems
Year:
2012

Citing 4
Cited 0

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Efficient Mapping of CORDIC Algorithm for OFDM-Based WLAN

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Maximum-likelihood symbol synchronization for IEEE 802.11a WLANs in unknown frequency-selective fading channels

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Efficient Inner Receiver Design for OFDM-Based WLAN Systems: Algorithm and Architecture

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Abstract

This paper deals with the design and implementation on FPGA of a receiver for OFDM-based WLAN. The circuit is particularized for IEEE 802.11a/g standards. The system includes frame detection, time and frequency synchronization, demodulation, equalization and phase tracking. The algorithms to be implemented for each task are selected taking into account performance, hardware cost and latency. Also, a fixed point analysis is made for each algorithm. Our objective is to maintain the PER loss below 0.5dB for a PER=10^-^2, 64-QAM and error correction. The whole system is composed of two main blocks (correlator and CORDIC) that are reused in different time intervals to perform all the necessary operations, so the required hardware resources are minimized. To verify it, the receiver is physically implemented and tested.