The SPARC architecture manual: version 8
The SPARC architecture manual: version 8
MIPS RISC architectures
A methodology for implementing highly concurrent data objects
ACM Transactions on Programming Languages and Systems (TOPLAS)
The SPARC architecture manual (version 9)
The SPARC architecture manual (version 9)
MC 68020 32-Bit Microprocessor User's Manual
MC 68020 32-Bit Microprocessor User's Manual
Notes on “A methodology for implementing highly concurrent data objects”
ACM Transactions on Programming Languages and Systems (TOPLAS)
A scalable mark-sweep garbage collector on large-scale shared-memory machines
SC '97 Proceedings of the 1997 ACM/IEEE conference on Supercomputing
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Recently, a novel pair of process synchronization instructions, load_linked and store_conditional, were introduced into the computing repertoire. These instructions were used to define two novel and intriguing protocols for process synchronization, a lock free and a wait free protocol; these protocols do not require critical sections, and can be used for fault-tolerant processing. Additionally, the lock free protocol guarantees that at least one process will always make progress, while the wait free protocol guarantees that all processes will make progress. Herlihy [1993] does a superb job of presenting and illustrating these concepts and ideas. However, there are a number of issues and errors concerning correctness, clarity, and completeness that were left unaddressed, and they are identified and resolved in this paper.