Computation vs. memory systems: pinning down accelerator bottlenecks

  • Authors:
  • Martha A. Kim;Stephen A. Edwards

  • Affiliations:
  • Department of Computer Science, Columbia University, New York, NY;Department of Computer Science, Columbia University, New York, NY

  • Venue:
  • ISCA'10 Proceedings of the 2010 international conference on Computer Architecture
  • Year:
  • 2010

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Abstract

The world needs special-purpose accelerators to meet future constraints on computation and power consumption. Choosing appropriate accelerator architectures is a key challenge. In this work, we present a pintool designed to help evaluate the potential benefit of accelerating a particular function. Our tool gathers cross-procedural data usage patterns, including implicit dependencies not captured by arguments and return values. We then use this data to characterize the limits of hardware procedural acceleration imposed by on-chip communication and storage systems. Through an understanding the bottlenecks in future accelerator-based systems we will focus future research on the most performance-critical regions of the design. Accelerator designers will also find our tool useful for selecting which regions of their application to accelerate.