Energy-efficient scheduling on heterogeneous multi-core architectures
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
Lucky scheduling for energy-efficient heterogeneous multi-core systems
HotPower'12 Proceedings of the 2012 USENIX conference on Power-Aware Computing and Systems
Kinship: efficient resource management for performance and functionally asymmetric platforms
Proceedings of the ACM International Conference on Computing Frontiers
Energy-aware thread co-location in heterogeneous multicore processors
Proceedings of the Eleventh ACM International Conference on Embedded Software
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Over the last decade, homogeneous multi-core processors emerged and became the de-facto approach for offering high parallelism, high performance and scalability for a wide range of platforms. We are now at an interesting juncture where several critical factors (smaller form factor devices, power challenges, need for specialization, etc) are guiding architects to consider heterogeneous chips and platforms for the next decade and beyond. Exploring heterogeneous architectures is challenging since it involves re-evaluating architecture options, OS implications and application development. In this paper, we describe these research challenges and then introduce a heterogeneous prototype platform called QuickIA that enables rapid exploration of heterogeneous architectures employing multiple generations of Intel processors for evaluating the implications of asymmetry and FPGAs to experiment with specialized processors or accelerators. We also show example case studies using the QuickIA research prototype to highlight its value in conducting heterogeneous architecture, OS and applications research.