A new methodology for accurate trace collection and its application to memory hierarchy performance modeling

A national trace collection and distribution resource

ACM SIGARCH Computer Architecture News

Facilitating level three cache studies using set sampling

Proceedings of the 32nd conference on Winter simulation

Using the BACH trace collection mechanism to characterize the SPEC 2000 integer benchmarks

Workload characterization of emerging computer applications

Selective Victim Caching: A Method to Improve the Performance of Direct-Mapped Caches

IEEE Transactions on Computers

Tradeoffs in the Design of Single Chip Multiprocessors

PACT '94 Proceedings of the IFIP WG10.3 Working Conference on Parallel Architectures and Compilation Techniques

Transaction processing workloads-a comparison to the SPEC benchmarks using memory hierarchy performance studies

MASCOTS '96 Proceedings of the 4th International Workshop on Modeling, Analysis, and Simulation of Computer and Telecommunications Systems