Parallel algorithms and VLSI architectures for stack filteringusing Fibonacci p-codes

  • Authors:

  • D.Z. Gevorkian;K.O. Egiazarian;S.S. Agaian;J.T. Astola;O. Vainio

  • Affiliations:

  • Inst. for Problems of Inf. & Autom., Acad. of Sci., Yerevan;-;-;-;-

  • Venue:
  • IEEE Transactions on Signal Processing
  • Year:
  • 1995

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Abstract

A parallel decompositional algorithm and VLSI architecture is proposed for computation of the output of a stack filter over a single window of input samples using Fibonacci p-codes. For a subclass of positive Boolean functions, a more efficient parallel algorithm and VLSI architecture for running stack filtering is also presented. The area-time complexities of the proposed designs are estimated