Envelope and phase delays correction in an EER radio architecture
Analog Integrated Circuits and Signal Processing
Optimization Algorithms for the Multiplierless Realization of Linear Transforms
ACM Transactions on Design Automation of Electronic Systems (TODAES)
| Hi-index | 35.68 |
We examine the use of efficient shift-and-add multiplier structures and multiplier blocks to reduce computational complexity in filter banks. This is more efficient than treating each bank filter separately. We also examine the Farrow (see Proc. Int. Symp. Circuits Syst. (ISCAS), p. 2641-2645) structure, which is used in interpolators. Applying multiplier blocks makes this structure cheaper than the more recognized Lagrange interpolator