A Comparison Design of Comb Decimators for Sigma-Delta Analog-to-Digital Converters
Analog Integrated Circuits and Signal Processing - Selected papers from the NORCHIP '98 Conference
Design of narrowband highpass FIR filters using sharpening RRS filter and IFIR structure
Practicing software engineering in the 21st century
Design of CIC roll-off compensation filter in a W-CDMA digital IF receiver
Digital Signal Processing
Design of wideband CIC compensator filter for a digital IF receiver
Digital Signal Processing
Sample rate conversion filter design for multi-standard software radios
Digital Signal Processing
WCNC'09 Proceedings of the 2009 IEEE conference on Wireless Communications & Networking Conference
Efficient comb decimation filter with sharpened magnitude response
WiCOM'09 Proceedings of the 5th International Conference on Wireless communications, networking and mobile computing
An economical class of droop-compensated generalized comb filters: analysis and design
IEEE Transactions on Circuits and Systems II: Express Briefs
Desensitized half-band filters
IEEE Transactions on Circuits and Systems Part I: Regular Papers
A novel two-stage nonrecursive architecture for the design of generalized comb filters
Digital Signal Processing
An improved wideband CIC filter design of software radio receivers
International Journal of Wireless and Mobile Computing
An improved class of multiplierless decimation filters: Analysis and design
Digital Signal Processing
Hi-index | 35.68 |
A new architecture for the implementation of high-order decimation filters is described. It combines the cascaded integrator-comb (CIC) multirate filter structure with filter sharpening techniques to improve the filter's passband response. This allows the first-stage CIC decimation filter to be followed by a fixed-coefficient second-stage filter, rather than a programmable filter, thereby achieving a significant hardware reduction over existing approaches. Furthermore, the use of fixed-coefficient filters in place of programmable-coefficient filters improves the overall throughput rate. The resulting architecture is well suited for single-chip VLSI implementation with very high data-sample rates. We discuss an example with specifications suitable for use in a wideband satellite communication subband tuner system and for signal analysis