A Comparison Design of Comb Decimators for Sigma-Delta Analog-to-Digital Converters

Authors:
Yonghong Gao;Lihong Jia;Jouni Isoaho;Hannu Tenhunen
Affiliations:
Electronic System Design Laboratory, Royal Institute of Technology, Electrum 229, 164 40, Sweden gaoyh@ele.kth.se;Electronic System Design Laboratory, Royal Institute of Technology, Electrum 229, 164 40, Sweden;Electronic System Design Laboratory, Royal Institute of Technology, Electrum 229, 164 40, Sweden;Electronic System Design Laboratory, Royal Institute of Technology, Electrum 229, 164 40, Sweden
Venue:
Analog Integrated Circuits and Signal Processing - Selected papers from the NORCHIP '98 Conference
Year:
2000

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Abstract

This paper presents a comparison design of comb decimators based on the non-recursive algorithm and the recursive algorithm. Compared with the recursive algorithm, the main advantage of the non-recursive algorithm is its abilities of reducing power consumption and increasing circuit speed especially when the decimation ratio and filter order are high. Based on the non-recursive algorithm, a decimator with programmable filter orders (3rd, 4th and 5th), decimation ratios (8, 16, 32 and 64) and input bits (1 and 2 bits) has been implemented in a 0.6 μm 3.3 V CMOS process. Its measured core power consumption is 44 mW at the oversampling rate of 25 MHz and its highest input data rate is 110 MHz.