Systolic block Householder transformation for RLS algorithm withtwo-level pipelined implementation

Authors:
K.R. Liu;S.-F. Hsieh;K. Yao
Affiliations:
Dept. of Electr. Eng., Maryland Univ., College Park, MD;-;-
Venue:
IEEE Transactions on Signal Processing
Year:
1992

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Abstract

The authors propose a systolic block Householder transformation (SBHT) approach to implement the HT on a systolic array and also propose its application to the RLS (recursive least squares) algorithm. Since the data are fetched in a block manner, vector operations are in general required for the vectorized array. However, a modified HT algorithm permits a two-level pipelined implementation of the SBHT systolic array at both the vector and word levels. The throughput rate can be as fast as that of the Givens rotation method. The present approach makes the HT amenable for VLSI implementation as well as applicable to real-time high-throughput applications of modern signal processing. The constrained RLS problem using the SBHT RLS systolic array is also considered