Share memory aware scheduler: balancing performance and fairness

  • Authors:

  • Xi Li;Gangyong Jia;Yun Chen;Zongwei Zhu;Xuehai Zhou

  • Affiliations:

  • University of Science and Technology of China (USTC), Hefei, China;University of Science and Technology of China (USTC), Hefei, China;University of Science and Technology of China (USTC), Hefei, China;University of Science and Technology of China (USTC), Hefei, China;University of Science and Technology of China (USTC), Hefei, China

  • Venue:
  • Proceedings of the great lakes symposium on VLSI
  • Year:
  • 2012

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Abstract

Optimizing system performance through scheduling has received a lot of attention. However, none of the existing approaches can balance the system performance improvement and the fair share of CPU time among threads. We present in this paper a share memory aware scheduler (SMAS). The key idea is to adopt thread group scheduling which partitions threads based on memory address space to reduce switching overhead and to give each thread a fair chance to occupy CPU time. There are three main contributions: 1) SMAS does well in balancing system performance and fairness among all threads; 2) to our knowledge, this is the first attempt to use share memory aware scheduler for system performance improvement; 3) we implement SMAS both in testbed and simulator for evaluation. The testbed results on a 2-core processor show that our proposed scheduler can improve performance of different performance parameters with neglected overhead in fairness, which reduced 0.128% in cache miss rate, 2.62% in run time, 13.15% in DTBL misses, 31.68% in ITLB misses and 46.15% in ITLB flushes maximum. Furthermore, our extensive simulation results for 4 and 8 cores demonstrate that SMAS is highly scalable.