Systolic Galois field exponentiation in a multiple-valued logic technique
Integration, the VLSI Journal
Systolic product-sum circuit for GF((22)m) using neuron MOSFETs
Integration, the VLSI Journal
Systolic product-sum circuit for GF((22)m) using neuron MOSFETs
Integration, the VLSI Journal
Systolic Galois field exponentiation in a multiple-valued logic technique
Integration, the VLSI Journal
| Hi-index | 0.00 |
Spiking neuron models, which represent information in the form of spatiotemporal patterns in spike pulse trains, have attracted much attention recently in the fields of computational neuroscience and artificial neural networks. The information processing abilities of spiking neuron models have been proven superior to those of the conventional analog-type (rate-coding) neural network models. In particular, the spike response model (SRM), which simplifies the biological neuron operation from the viewpoint of spike response, is important for VLSI implementation and various applications. In the SRM, the generation of post-synaptic potentials (PSPs) is essential. The conventional CMOS devices require complicated circuits in order to realize the function of SRM neurons. In this paper, a new device structure using a MOSFET with multinanodot floating-gate arrays is proposed for the synapse component of SRM neurons. This structure can operate at room temperature, as it utilizes thermal-noise-assisted tunneling between nanodots. The structure generates PSPs by taking advantage of the delay in electron movement due to stochastic tunneling processes. The results of single-electron circuit simulation demonstrate the generation of PSPs. The proposed structure has not yet been fabricated. The aim of this paper is to propose guidelines for the development of new nanoscale devices and fabrication technology for intelligent information processing such as that achieved in the human brain.