A Ternary Systolic Product-Sum Circuit for GF(3**m) using Neuron MOSFETs
ISMVL '96 Proceedings of the 26th International Symposium on Multiple-Valued Logic
Multiple-Valued Galois Field S/D Trees for GFSOP Minimization and Their Complexity
ISMVL '01 Proceedings of the 31st IEEE International Symposium on Multiple-Valued Logic
Constructing Composite Field Representations for Efficient Conversion
IEEE Transactions on Computers
Integration, the VLSI Journal
Divided Difference Methods for Galois Switching Functions
IEEE Transactions on Computers
Systolic Multipliers for Finite Fields GF(2m)
IEEE Transactions on Computers
Galois Switching Functions and Their Applications
IEEE Transactions on Computers
A multinanodot floating-gate MOSFET circuit for spiking neuron models
IEEE Transactions on Nanotechnology
Systolic Galois field exponentiation in a multiple-valued logic technique
Integration, the VLSI Journal
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A quaternary systolic product-sum computation circuit for GF((2^2)^m) using voltage-mode vMOSFETs is presented. The design is composed of four basic cells connected in a pipelined fashion. Each basic cell is composed of 2 Galois field adders, 2 Galois field multipliers, and 7 flip-flops. The circuit was simulated using Affirma Analog Circuit Design Environment tool supplied by Cadence, and it has shown to perform correctly. The quaternary circuit for GF((2^2)^2) shows a significant amount of savings in both transistor count and number of connections compared to the one that uses the binary field GF(2^4).