Systolic product-sum circuit for GF((22)m) using neuron MOSFETs
Integration, the VLSI Journal
Systolic product-sum circuit for GF((22)m) using neuron MOSFETs
Integration, the VLSI Journal
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The idea of S/D trees for binary logic is a general concept that found its main application in ESOP minimization and the generation of new diagrams and canonical forms. S/D trees demonstrated their power by generating forms that include a minimum Galois-Field-Sum-of-Products (GFSOP) circuits for binary and ternary radices. Galois Field of quaternary radix has some interesting properties. An extension of the S/D trees to GF(4) is presented here. A general formula to calculate the number of Inclusive Forms (IFs) per variable order for an arbitrary Galois field radix and arbitrary number of variables is derived. A new fast method to count the number of IFs for an arbitrary Galois field radix and functions of two variables is introduced; the IFn,2 Triangles. This research is useful to create an efficient GFSOP minimizer for reversible logic.