A Ternary Systolic Product-Sum Circuit for GF(3**m) using Neuron MOSFETs

Authors:
Noriaki Muranaka;Shigenobu Arai;Shigeru Imanishi;D. Michael Miller
Affiliations:
-;-;-;-
Venue:
ISMVL '96 Proceedings of the 26th International Symposium on Multiple-Valued Logic
Year:
1996

Citing 0
Cited 4

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Systolic Galois field exponentiation in a multiple-valued logic technique

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Abstract

In this paper, we present a ternary systolic product-sum computation circuit for GF(3**m) using voltage-mode neuron MOSFETs. The required subcircuits are discussed which together form a basic cell. The overall design which connects basic cells in a systolic manner, thereby making effective use of pipelining, is shown. SPICE simulations of the central part of the basic cell are presented which demonstrate its proper behaviour. The ternary circuit for GF(3**2) is compared to the binary circuit for GF(2**3) and is shown to be superior both in terms of the number of transistors and the number of connections.