The ESTEREL synchronous programming language: design, semantics, implementation
Science of Computer Programming
UPPAAL—a tool suite for automatic verification of real-time systems
Proceedings of the DIMACS/SYCON workshop on Hybrid systems III : verification and control: verification and control
Integrating Multimedia Applications in Hard Real-Time Systems
RTSS '98 Proceedings of the IEEE Real-Time Systems Symposium
Regular Specifications of Resource Requirements for Embedded Control Software
RTAS '08 Proceedings of the 2008 IEEE Real-Time and Embedded Technology and Applications Symposium
Execution Strategies for PTIDES, a Programming Model for Distributed Embedded Systems
RTAS '09 Proceedings of the 2009 15th IEEE Symposium on Real-Time and Embedded Technology and Applications
EMSOFT '09 Proceedings of the seventh ACM international conference on Embedded software
Compensation of networked control systems with time-delay and data packet losses
CCDC'09 Proceedings of the 21st annual international conference on Chinese control and decision conference
Network calculus: a theory of deterministic queuing systems for the internet
Network calculus: a theory of deterministic queuing systems for the internet
Integrated scheduling and synthesis of control applications on distributed embedded systems
Proceedings of the Conference on Design, Automation and Test in Europe
Control-quality driven design of cyber-physical systems with robustness guarantees
Proceedings of the Conference on Design, Automation and Test in Europe
Model-based development and verification of control software for electric vehicles
Proceedings of the 50th Annual Design Automation Conference
Co-design of control and platform with dropped signals
Proceedings of the ACM/IEEE 4th International Conference on Cyber-Physical Systems
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We propose a performance verification technique for cyber-physical systems that consist of multiple control loops implemented on a distributed architecture. The architectures we consider are fairly generic and arise in domains such as automotive and industrial automation; they are multiple processors or electronic control units (ECUs) communicating over buses like FlexRay and CAN. Current practice involves analyzing the architecture to estimate worst-case end-to-end message delays and using these delays to design the control applications. This involves a significant amount of pessimism since the worst-case delays often occur very rarely. We show how to combine functional analysis techniques with model checking in order to derive a delay-frequency interface that quantifies the interleavings between messages with worst-case delays and those with smaller delays. In other words, we bound the frequency with which control messages might suffer the worst-case delay. We show that such a delay-frequency interface enables us to verify much tigher control performance properties compared to what would be possible with only worst-case delay bounds.